The present invention relates to a semiconductor device including a fuse circuit which can be disconnected by laser ablation and a method for fabricating the semiconductor device.
Semiconductor devices, such as memory devices of DRAMs, SRAMs, etc., logic devices, etc., are constituted by a very large number of elements, and a part of the circuit or of the memory cells are often inoperative due to various cause in their fabrication processes. In this case, when semiconductor devices partially defective circuits or memory cells are generally regarded as defective devices, the semiconductor devices have low fabrication yields, which might lead to fabrication cost increase. In view of this, recently such defective semiconductor devices have defective circuits or defective memory cells replaced by redundant circuits or redundant memory cells which have been prepared in advance, to create properly functioning devices. In some semiconductor devices, a plurality of circuits having functions different from each other are formed integrated and later those of certain functions are replaced, and in other semiconductor devices prescribed circuits are formed, and later characteristics of the semiconductor devices are adjusted. In such reconstruction of semiconductor devices, usually a fuse circuit having a plurality of fuses is formed on the semiconductor devices, and after operation tests, etc., the fuses are disconnected by laser beam irradiation.
A conventional semiconductor device including a fuse circuit and a method for fabricating the same will be explained with reference to FIGS. 25A-25C. FIG. 25A is a diagrammatic sectional view of the conventional semiconductor device, which shows a structure thereof. FIG. 25B is a plan view of the conventional semiconductor device, which shows the structure thereof. FIG. 25C is a diagrammatic sectional view of the conventional semiconductor device with a fuse disconnected, which shows the structure thereof.
A fuse 202 is formed on a substrate 200, connected to a prescribed circuit for replacing the circuit. An inter-layer insulation film 204 for covering the fuse 202 is formed thereon. An interconnection layer 206 is formed on the inter-layer insulation film 204, connected to the fuse 202 therethrough. A plurality of the fuses 202 are formed on the substrate 200 at a prescribed pitch (FIGS. 25A and 25B). Furthermore, there is formed a passivation film 211 which covers the interconnection layer 206 and is thinner partially on the fuses 202.
To disconnect the fuse 202 in such fuse circuit, a laser beam 208 is irradiated to a region where the fuse is formed, whereby the fuse 202 is rapidly heated by its absorbed energy to a high temperature and undergoes laser explosion (FIG. 25C).
Here to further micronize the semiconductor device, it is necessary to further decrease a pitch between the fuses 202, but a pitch P of the fuses 202 is determined by a spot size 210 of the laser beam 208 and alignment accuracy of the laser beam 208.
A spot size of the laser beam 208 has a lower limit which is determined by a wavelength of the laser beam 208, and the spot size 208 can be decreased as the laser beam has a shorter wavelength. However, when a wavelength of the laser beam is too short, there is a risk that the laser beam may pass through a region where the fuse 202 is not formed, arrives at the base semiconductor substrate and is absorbed therein, and cause thermal laser explosion. In a case that the semiconductor substrate is silicon, the laser beam has an about 1 .mu.m wavelength, at which silicon substrates absorb small amounts of laser beams. That is, a lower limit is about 1.5-2.0 .mu.m in spot size.
On the other hand, alignment accuracy is required for the prevention of a disadvantage that the base silicon substrate is damaged if the laser explosion regions overlap each other in blowing both fuses 202 adjacent to each other and also for the prevention of a disadvantage that in disconnecting one of fuses 202 adjacent to each other, the other is damaged or blown. Usually a lower limit of the alignment accuracy is about 0.5 .mu.m.
Thus, a lower limit of the fuse pitch of the above-described conventional fuse disconnecting method is about 2.0-2.5 .mu.m.
As a method for narrowing a pitch P of the fuses, a method using a photoresist is known.
In the method using a photoresist, a photoresist 212 is formed in a step before the step of forming a passivation film 211 of the semiconductor device shown in FIG. 25A (FIG. 26A), a laser beam 208 whose power is low enough not to cause laser explosion is irradiated to expose the photoresist 212 (FIG. 26B), the exposed photoresist 212 is developed to remove the photoresist 212 in the exposed region 214 (FIG. 26C), a fuse 202 is removed by the usual etching process with the photoresist 212 as a mask (FIG. 26D), and the fuse 202 is disconnected with the photoresist 212 as a mask (FIG. 26D).
According to this method, the laser beam 208 may have a power which is sufficient only to expose the photoresist 212, and it is not necessary that the power is high enough to laser explode the fuse 202 or the semiconductor substrate. Accordingly, the laser beam 208 can easily have a shorter wavelength and can have a spot size 210 which is decreased in accordance with a wavelength of the laser beam 208. Accordingly, a fuse pitch P, which is determined by a spot size 210 of the laser beam can be decreased.
However, the method using a photoresist must additionally include a photoresist application step and a photoresist development step, a fuse etching step and a photoresist releasing step. Conventionally, it has caused no trouble that the test process following completion of the wafer process has lower cleanliness in comparison with that in the wafer process clean room, but in a case that a process, such as etching, formation of a passivation film or others, is performed after the test, it is necessary to perform the test process in a clean room of high cleanliness so that dust on wafers does not pollute the etching system, or an etching system which is exclusively used for the fuse disconnection is installed, which leads to higher fabrication costs rather than simple increase of fabrication steps.
As described above, in the conventional fuse disconnecting method, it is difficult to narrow a fuse pitch corresponding to increased integration of a semiconductor device while depressing increase of fabrication steps and fabrication costs.